Various testing techniques are used to test multiple cores of a system-on-chip (SoC) and to test interfaces between the cores. It is desired to reduce test time of the SoC with minimal effect on functional timing of the SoC. Currently used test techniques make use of scan chains, for example a natural bounding chain and a wrapper scan chain, for isolating the cores of the SoC and enabling testing. However, the wrapper scan chain increases area of the integrated circuit by adding a flip-flop and a multiplexer along a functional path, and also impacts the functional timing. The natural bounding chain is formed by stitching core flip-flops that meet certain criteria. If the core is poorly registered, then the number of flip-flops forming the natural bounding chain is high and hence the test time is also high.
In light of the foregoing discussion there is a need for an efficient method and system for testing the SoC that overcomes one or more of the above-mentioned issues.